The invention relates to a configuration for testing an integrated semiconductor memory which has a control I/O terminal in addition to data I/O terminals, in which case, during the test, test signals are prescribed by a test unit and fed to the module to be tested and response signals output by the module to be tested are received for evaluation.
Before they are supplied, integrated semiconductor memories are tested by the manufacturer using costly memory test systems on which the functionality of the memory chips is checked by test programs. In this case, signals with precisely defined voltage levels are applied at exactly defined instants to the semiconductor memories to be tested. The response signals generated by the semiconductor memory are read into the test unit and compared with expected signal values.
On account of the high frequencies at which the memory modules operate nowadays, the specification of the chips requires a high accuracy of the signals. Thus, in double data rate (DDR) memories, for example, signal specifications of the order of magnitude of 400 picoseconds are customary even today. The production and memory test systems used must therefore satisfy extremely stringent technical requirements, which leads to correspondingly high production and test costs. In the case of extremely high-frequency memory modules, such as the above-mentioned DDR memories, the test costs already amount to up to 30% of the total manufacturing costs. For this reason, test concepts are being advanced in which as many memory modules as possible can be tested in parallel.
DDR-SDRAMs utilize for synchronization of the data transfer not only the normal system clock but an additional bi-directional strobe signal. This signal runs in parallel with the data and is used for the memory module as a reference for the validity of the transferred data and thereby enables a high-speed data transfer.
In the case of a read command, the DDR-SDRAM generates and controls the bi-directional strobe signal and indicates the validity of the data to the connected chip set with the rising and falling edges. In the case of a write operation, the chip set generates and controls the strobe signal and thus signals the validity of the data to be read in to the memory module with both edges. Roughly speaking by utilizing both clock edges, the effective data transfer rate is thus doubled compared with a single data rate (SDR) chip.
During the functional tests of the DDR memory modules, the problem arises that each bi-directional strobe signal DQS occupies an additional I/O test channel. However, such I/O test channels are available only in a very limited number on customary test adapters. By way of example, a test adapter from the company Advantest for conventional single data rate modules provides 72 bi-directional I/O channels per memory module, sufficient for nine memory modules of a module having eight data lines in each case. An entire test head can then be used to test eight memory modules in parallel.
When testing DDR memory, not only the bi-directional data lines but also the bi-directional DQS terminal must be tested for functionality. (8+1)xc3x979=81 I/O channels are then required per memory module instead of 8xc3x979=72 I/O channels in the case of single data rate memories. The higher number of I/O channels per module requires a new division of the assignment of the channels on the test head, which in practice leads to a halving of the test capacity.
Japanese Patent Abstract JP 2000207900 A discloses a test configuration for a DDR memory in which a circuit is integrated into the module to be tested, which circuit receives test control signals of a control channel of the test unit and forwards them as internal control signal.
It is accordingly an object of the invention to provide a configuration for testing an integrated semiconductor memory and a method for testing the memory which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which testing of semiconductor memories is performed with an additional bi-directional control terminal in a simple and cost-effective manner and in a highly parallel manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for assisting in testing a memory having a control I/O terminal and data I/O terminals. During a test, a test unit generates test signals to be fed to the memory and response signals output by the memory are received for evaluation. The configuration contains a circuit disposed and connected into a signal path between the test unit and the memory to be tested. The circuit includes a data writing device for receiving test data from data I/O channels of the test unit and for outputting the test data to the data I/O terminals of the memory to be tested, a control signal writing device for receiving test control signals from a control channel of the test unit and for outputting the test control signals to the control I/O terminal of the memory to be tested, and a reading/coding device for receiving response data signals from the data I/O terminals and response control signals from the control I/O terminal of the memory to be tested. The reading/coding device codes the response data signals with the response control signals and outputs coded response signals to the data I/O channels of the test unit. The reading/coding device is connected to the data writing device and to the control signal writing device.
The invention is thus based on the concept that, during writing, the bi-directional control terminal of the module to be tested is supplied with the signal of a unidirectional control channel of the test unit and, during reading, the response control signals generated are output to the test unit only indirectly via a coding of the response data signals. As a result, the functionality of the bi-directional control terminal can be tested without an additional I/O tester channel having to be provided.
The reading/coding device, for coding purposes, preferably combines at least the response data signals of one data I/O terminal with the response control signals of the control I/O terminal with an XOR combination. The reading/coding device particularly preferably carries out an XOR combination of the response data signals of all the data I/O terminals with the response control signals of the control I/O terminal. When a plurality of the data I/O terminals are combined with the control signals of the control I/O terminal, it is possible, in the error situation, to ascertain particularly reliably whether one of the data I/O terminals or the control I/O terminal is to be assessed as defective.
The data writing devices, the control signal writing device and the reading/coding device expediently receive command signals of the test unit for distinguishing between read and write accesses to the module to be tested.
In a preferred refinement, the data writing device contains a delay element for the adjustable delay of the test data signals. As an alternative or in addition, the control signal writing device advantageously contains a delay element for the adjustable delay of the test control signals.
It may be expedient to integrate the circuit on the module to be tested. The test logic can then be activated via a test mode, for example.
As an alternative, the circuit may be mounted on a test adapter that can be connected to the test unit. The circuit can then be fitted on the module or chip base.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for testing a memory having a control I/O terminal and data I/O terminals. The method includes the steps of: providing test data signals at data I/O channels of a test unit, providing a test control signal at a control channel of the test unit, and applying the test data signals to the data I/O terminals and the test control signal to the control I/O terminal of the memory to be tested. Response data signals are received from the data I/O terminals and response control signals are received from the control I/O terminal of the memory to be tested. The response data signals are coded with the response control signals. The coded response signals are output to the data I/O channels of the test unit.
In accordance with an added mode of the invention, there is the step of coding at least the response data signals of one of the data I/O terminals with the response control signals of the control I/O terminal by XOR combination.
In accordance with a further mode of the invention, there is the step of applying the test data signals and/or the test control signal with an adjustable temporal offset to at least one of the data I/O terminals and the control I/O terminal of the memory to be tested.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration for testing an integrated semiconductor memory and a method for testing the memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.